1. Field of the Invention
The disclosures herein relate to a wiring substrate having a projection projecting from a surface of the wiring substrate, a semiconductor package having such a wiring substrate, and methods of making the wiring substrate and the semiconductor package.
2. Description of the Related Art
A semiconductor package having a semiconductor chip mounted on a wiring substrate via solder bumps or the like is known to those skilled in the art. For this type of semiconductor package, it is important to improve the reliability of connection between the wiring substrate and the semiconductor chip. In related-art semiconductor packages, metal layer portions are formed on a wiring substrate to protrude from a surface of the wiring substrate, and solder bumps are formed on these metal layer protruding portions for the purpose of improving the reliability of connection between the wiring substrate and the semiconductor chip. In the following, a description will be given of an example of a related-art wiring substrate on which metal layer portions projecting from a surface of the wiring substrate are formed.
FIG. 1 is a cross-sectional view illustrating an example of a related-art wiring substrate. In FIG. 1, a wiring substrate 100 includes a first insulating layer 130a, a second insulating layer 130b, a third insulating layer 130c, a first interconnection layer 140a, a second interconnection layer 140b, a protruding metal layer 160, and solder bumps 170.
In the wiring substrate 100, the first interconnection layer 140a formed in the first insulating layer 130a and the second interconnection layer 140b formed in the second insulating layer 130b are electrically connected to each other through first via holes 150a. The first insulating layer 130a is formed on a surface of the second insulating layer 130b and on the first interconnection layer 140a, and has openings 130x that expose part of the first interconnection layer 140a. 
The third insulating layer 130c is formed on the other surface of the second insulating layer 130b to cover the second interconnection layer 140b. The protruding metal layer 160 is formed in openings 130y of the third insulating layer 130c to partly project from a surface 100a of the wiring substrate 100. The protruding metal layer 160 includes a Cu layer 161 and an Ni layer 162. The Cu layer 161 protrudes approximately 30 μm from the surface 100a of the wiring substrate 100. The Ni layer 162 having a thickness of approximately 5 μm is formed on the surface of the Cu layer 161. The Cu layer 161 and the second interconnection layer 140b are electrically connected to each other through second via holes 150b. The solder bumps 170 are formed on the protruding metal layer 160.
In the following, a method of making the wiring substrate 100 will be described. FIGS. 2 through 6 are drawings illustrating an example of a related-art method of making a wiring substrate. In FIGS. 2 through 6, the same elements as those of FIG. 1 are referred to by the same numerals, and a description thereof may be omitted.
In the process step illustrated in FIG. 2, a carrier metal (i.e., metal plate) 110 comprised of SUS (Stainless Used Steel) having a thickness of approximately 500 μm is provided. On a surface 110a of the carrier metal 110, an etching resist layer 120a having a predetermined pattern is formed, and openings 120x are farmed through the photolithography method at positions corresponding to the positions where the protruding metal layer 160 is to be formed in the wiring substrate 100. Further, an etching resist layer 120b is formed to cover a back surface 110b of the carrier metal 110.
In the process step illustrated in FIG. 3, etching solution to dissolve SUS is sprayed to etch the exposed areas of the surface 110a of the carrier metal 110 in the openings 120x of the etching resist layer 120a. As a result, holes 110x having a depth of approximately 20 μm and having a substantially circular plan shape are formed in the surface 110a of the carrier metal 110.
In the process step illustrated in FIG. 4, a protruding metal layer 160a protruding beyond the surface 110a of the carrier metal 110 is formed in the holes 110x. Specifically, an Au electroplating process is performed to form an electrolytic Au plate, thereby forming an Au plate layer 163 having a thickness of approximately 0.5 μm on the inner wall surfaces of the openings 110x. An Ni electroplating process is then performed to form an electrolytic Ni plate, thereby forming an Ni plate layer 162 having a thickness of approximately 5 μm on the Au plate layer 163.
Further, a Cu electroplating process is performed to form a Cu layer 161 having a thickness (height) of approximately 30 μm on the Ni layer 162, thereby filling holes formed by the Ni layer 162 with the Cu layer 161. In this process step, it is preferable to use a Cu electrolytic plating solution for use in filled-via formation in order to readily fill the holes formed by the Ni layer 162. Through the three electroplating steps described above, the protruding metal layer 160a including the Cu layer 161, Ni layer 162, and Au layer 163 is formed. The protruding metal layer 160a has the Au layer 163 added to the protruding metal layer 160.
In the process step illustrated in FIG. 5, upon removal of the etching resist layer 120a and 120b illustrated in FIG. 4, a third insulating layer 130c having second via holes 150b and openings 130y at the positions of the protruding metal layer 160a is formed on the surface 110a of the carrier metal 110 and on the protruding metal layer 160a. Further, a second interconnection layer 140b electrically connected through the second via holes 150b to the Cu layer 161 of the protruding metal layer 160a is formed on the third insulating layer 130c. 
After this, a second insulating layer 130b having the first via holes 150a is formed on the third insulating layer 130c to cover the second interconnection layer 140b. Moreover, a first interconnection layer 140a electrically connected through the first via holes 150a to the second interconnection layer 140b is formed on the second insulating layer 130b. Further, the first insulating layer 130a having openings 130x to expose part of the first interconnection layer 140a is formed on the second insulating layer 130b to partly cover the first interconnection layer 140a. 
In the process step illustrated in FIG. 6, etching is performed to remove the entirety of the carrier metal 110 illustrated in FIG. 5, thereby exposing the entirety of the surface 100a of the wiring substrate 100 and the protruding metal layer 160a. After this, the solder bumps 170 are formed on the protruding metal layer 160a (see FIG. 1). In this process, the Au layer 163 would diffuse into the solder. In consideration of this, the solder bumps 170 are formed on the Ni layer 162 (i.e., on the protruding metal layer 160). In this manner, the wiring substrate 100 illustrated in FIG. 1 is manufactured.
The wiring substrate 100 has the protruding metal layer 160 protruding beyond the surface 100a of the wiring substrate 100 from inside the opening 130y of the third insulating layer 130c. The solder bumps 170 are formed on the protruding metal layer 160.
FIG. 7 is a cross-sectional view illustrating another example of a related-art wiring substrate. In FIG. 7, a wiring substrate 200 includes an etching stop layer 210b, a first interconnection layer 220, a CU layer 240, a second interconnection layer 250, an Ni layer 260, a first insulating layer 270, a second insulating layer 270a, a protruding metal layer 280, a reinforcement part 290, and solder bumps 300.
In the wiring substrate 200, the first interconnection layer 220 formed in the first insulating layer 270 and the second interconnection layer 250 formed in the second insulating layer 270a are electrically connected to each other through the CU layer 240 and the Ni layer 260. The etching stop layer 210b is formed on the first interconnection layer 220. The protruding metal layer 280 is formed on the etching stop layer 210b to project from a surface 200a of the wiring substrate 200. The solder bumps 280 are formed on the protruding metal layer 280. The second insulating layer 270a is formed on the first insulating layer 270 and on the second interconnection layer 250, and has openings 270x that expose part of the second interconnection layer 250.
In the following, a method of making the wiring substrate 200 will be described. FIGS. 8 through 12 are drawings illustrating another example of a related-art method of making a wiring substrate. In FIGS. 8 through 12, the same elements as those of FIG. 7 are referred to by the same numerals, and a description thereof may be omitted.
In the process step illustrated in FIG. 8, a metal substrate 210 having three layers is provided. The metal substrate 210 includes a metal layer 210a, the etching stop layer 210b, and a metal layer 210c. The metal substrate 210a is made of copper or copper alloy, and is formed in a film shape having a thickness of about 80 to 150 μm, for example. The etching stop layer 210b is made of a material having a sufficient etching selectivity ratio relative to copper or copper alloy when etching (e.g., etching using a hydrochloric-acid-based etching solution) is performed with respect to the copper or copper alloy. The metal layer 210c is a thin metal film made of copper stacked on the surface of the etching stop layer 210b. This metal layer 210c is to turn into the first interconnection layer 220.
In the process step illustrated in FIG. 9, the metal layer 210c of the metal substrate 210 having the three layer structure is patterned by photo-etching to form the first interconnection layer 220. A circuitry substrate 230 is then positioned relative to the metal substrate 210. The circuitry substrate 230 includes a metal layer 210d, the Ni layer 260, and the CU layer 240 stacked one over another in this order, with the first insulating layer 270 covering the surface thereof. It should be noted, however, the CU layer 240 is exposed through the first insulating layer 270. The metal layer 210d is to turn into the second interconnection layer 250.
In the process step illustrated in FIG. 10, the circuitry substrate 230 is stacked on the metal substrate 210. Specifically, the CU layer 240 of the circuitry substrate 230 is thermal-compression-bonded to the first interconnection layer 220 of the metal substrate 210 via the first insulating layer 270. At positions other than the positions of the CU layer 240, the circuitry substrate 230 and the metal substrate 210 are bonded to each other via the first insulating layer 270.
In the process step illustrated in FIG. 11, the metal layer 210d of the circuitry substrate 230 is patterned by photo-etching to form the second interconnection layer 250. The second insulating layer 270a is formed on the first insulating layer 270 and on the second interconnection layer 250, and has the openings 270x that expose part of the second interconnection layer 250. Ni plating or Au plating may be applied to the second interconnection layer 250 exposed through the opening 270x. 
In the process step illustrated in FIG. 12, the metal layer 210a made of copper illustrated in FIG. 11 is selectively etched from the back side to form the protruding metal layer 280 and the reinforcement part 290. A solder film (e.g., 10-to-50-μm thick) 300 is an etching mask used for the selective etching, and is formed by plating. The solder film 300 may be patterned through selective removal by alkali etching using a resist layer or the like as a mask. The solder film 300 is then used as an etching mask in the etching process that forms the protruding metal layer 280 and the reinforcement part 290. A reflow process is then applied to the solder film 300 to form the solder bumps 300, thereby forming the wiring substrate 200 illustrated in FIG. 7.
As described above, the wiring substrate 200 has the protruding metal layer 280 protruding from the surface 200a of the wiring substrate 200. The solder bumps 300 are formed on the protruding metal layer 280.
A metal protruding layer formed on a related-art wiring substrate serves as a reliable connection terminal that has a sufficient height. While this is the case, it is difficult to maintain this reliability when shortening the interval between adjacent portions of the metal protruding layer. This problem will be described in the following by referring to the relevant drawings.
In FIG. 3 and the like, the holes 110x formed by etching the carrier metal 110 are illustrated as having a rectangular cross-sectional shape. It is known, however, that their actual cross-sectional shape is not a rectangle. FIG. 13 is a drawing illustrating an example of the actual shape of holes formed by etching. As illustrated in FIG. 13, the holes 110y formed by etching do not have a rectangular cross-section taken on a plane parallel to the XZ plane as do the holes 110x, but have a round cross-section.
Since etching advances not only in the Z direction but also in the X direction and in the Y direction, a maximum diameter φ1 of the holes 110y at the etching resist layer 120a is larger than a maximum diameter φ2 of the openings 120x, assuming that the openings 120x has a circular plan shape (as viewed in the Z direction). Further, the maximum diameter φ1 of the holes 110y increases as a maximum depth D1 of the holes 110y increases. This gives rise to a problem especially when the pitch between the adjacent holes 110y shortens. This will be described by referring to FIG. 14.
FIG. 14 is a drawing illustrating an example of shortened pitches between adjacent holes illustrated in FIG. 13. As illustrated in FIG. 14, the shorter the pitch P1 between adjacent holes 110y, the higher the risk of having the adjacent holes 110y coming in contact with each other. In order for the adjacent holes 110y not to come in contact with each other, the maximum depth D1 may be required to be shallow. Because of this, it is difficult to provide the holes 110y formed by etching with a large aspect ratio (D1/φ1). Since the protruding metal layer 160 is formed in the holes 110y, it is difficult to form the protruding metal layer 160 having a large aspect ratio.
Further, the protruding metal layer 280 of the wiring substrate 200 is formed by etching as are the holes 110x of the wiring substrate 100, so that its cross-sectional shape is not rectangular as illustrated in FIG. 7 and the like. As illustrated in FIG. 7 and the like, the diameter of the top end surface of the protruding metal layer 280 is smaller than the diameter of its bottom surface on the etching stop layer 210b. Accordingly, an attempt to increase the area size of the top end surface of the protruding metal layer 280 for the purpose of improving the reliability of connection may increase the risk of having the adjacent portions of the protruding metal layer 280 coming in contact with each other. In order for the adjacent portions of the protruding metal layer 280 not to come in contact with each other, the height of the protruding metal layer 280 may be required to be small. Because of this, it is difficult to provide each piece of the protruding metal layer 280 formed by etching with a large aspect ratio.
As described above, the related-art methods of manufacturing a wiring substrate use an etching process to form a protruding metal layer, which prevents the cross-sectional shape of the protruding metal layer from being a rectangular shape, thereby failing to provide a large aspect ratio. As a result, pitches between adjacent portions of the protruding metal layer cannot be shortened while ensuring that the protruding metal layer serves as reliable connection terminals having a sufficient height. Conversely, if pitches between adjacent portions of the protruding metal layer are to be shortened, the height of the protruding metal layer needs to be lowered, which results in the reliability of connection being reduced.    [Patent Document 1] Japanese Patent Application Publication No. 2003-218286    [Patent Document 2] Japanese Patent Application Publication No. 2002-43506    [Patent Document 3] Japanese Patent Application Publication No. 2001-177010